module tb_top;

    bit PCLK;
    bit PRESETn;

    clk_rst_interface vifclk(PRESETn, PCLK);
    interface_apb            apb_if  (PCLK,PRESETn);
    interface_uart           uart_if (PCLK,PRESETn);

    /* ============================================= *\
                        DUT
    \* ============================================= */
    apb_uart_top  dut_top (
        .PCLK       (PCLK           ),
        .PRESETn    (PRESETn        ),
        .PSELx      (apb_if.PSELx   ),
        .PENABLE    (apb_if.PENABLE ),
        .PWRITE     (apb_if.PWRITE  ),
        .PREADY     (apb_if.PREADY  ),
        .PSLVERR    (apb_if.PSLVERR ),
        .PWDATA     (apb_if.PWDATA  ),
        .PADDR      (apb_if.PADDR   ),
        .PRDATA     (apb_if.PRDATA  ),
        .Tx         (uart_if.rxd    ),
        .RX         (uart_if.txd    )
    );

    /* ============================================= *\
                        ASSERT
    \* ============================================= */
    apbuart_property assertions (
        .PCLK       (PCLK           ),
        .PRESETn    (PRESETn        ),
        .PSELx      (apb_if.PSELx   ),
        .PENABLE    (apb_if.PENABLE ),
        .PWRITE     (apb_if.PWRITE  ),
        .PREADY     (apb_if.PREADY  ),
        .PSLVERR    (apb_if.PSLVERR ),
        .PWDATA     (apb_if.PWDATA  ),
        .PADDR      (apb_if.PADDR   ),
        .PRDATA     (apb_if.PRDATA  )            
    );
  
  initial begin 
    uvm_config_db # (virtual interface_apb)::set(uvm_root::get(),"*","apb_vif",apb_if);
    uvm_config_db # (virtual interface_uart)::set(uvm_root::get(),"*","uart_vif",uart_if);
    uvm_config_db # (virtual clk_rst_interface)::set(uvm_root::get(),"*","vifclk",vifclk);
    $fsdbDumpfile("tb.fsdb"); 
    $fsdbDumpvars(0, tb_top);
  end

  initial
    run_test(); // built in func...you can give test name as argument
endmodule
